The pursuit of making computing systems more powerful and more power efficient has led to advancement in interface communications to improve throughput without increasing, and ideally reducing, energy consumption. Often, as clock speeds increase, a desire to increase data transition times on interface busses to match the faster clock speeds exists. Future double data rate (DDR) dynamic random-access memory (DRAM) performance targets will soon exceed DRAM transistor switching capabilities. Some systems have implemented data encoding and special purpose, multi-level (e.g., more than two levels) bus architectures to increase throughput over an interface bus. However, these special purpose architectures increase cost and complexity, and require additional input/output (I/O) pins.